Azad Naeemi - Dissemin

Papers authored by Azad Naeemi

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2015 S. Rakheja, A. Ceyhan, A. Naeemi

Interconnect considerations: Interconnect considerations

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2014 Chenyun Pan, Saibal Mukhopadhyay, Azad Naeemi

System-level chip/package co-design for multi-core processors implemented with power-gating technique

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Rose Peng, Bill Dorn, Azad Naeemi

, Nassim Jafarinaimi

Interactive visualizations for teaching quantum mechanics and semiconductor physics

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Nickvash Kani, Azad Naeemi

Wiring resource minimization for physically-complex Network-on-Chip architectures

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Sourav Dutta

, Dmitri E. Nikonov

, Sasikanth Manipatruni, Ian A. Young, Azad Naeemi

SPICE Circuit Modeling of PMA Spin Wave Bus Excited Using Magnetoelectric Effect

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Sou-Chi Chang, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Azad Naeemi

Design and Analysis of Si Interconnects for All-Spin Logic

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Vachan Kumar, Li Zheng, Rohit Sharma, Erdal Uzunlar, Li Zheng, Rizwan Bashirullah, Paul Kohl, Muhannad S. Bakir, Azad Naeemi

Airgap Interconnects: Modeling, Optimization, and Benchmarking for Backplane, PCB, and Interposer Applications

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Sou-Chi Chang, Sou-Chi Chang, Rouhollah Mousavi Iraei, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Azad Naeemi

Design and Analysis of Copper and Aluminum Interconnects for All-Spin Logic

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Vachan Kumar, Ramy Nashed, Kevin Brenner, Romeil Sandhu, Azad Naeemi

System level analysis and benchmarking of graphene interconnects for low-power applications

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Azad Naeemi

SPICE models for metallic all-spin-logic devices and interconnects

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Azad Naeemi

, Ahmet Ceyhan, Vachan Kumar, Chenyun Pan, Rouhollah M. Iraei, Shaloo Rakheja

BEOL Scaling Limits and Next Generation Technology Prospects

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Chenyun Pan, Azad Naeemi

System-level variation analysis for interconnection networks

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Phillip Bonhomme, Sasikanth Manipatruni, Rouhollah M. Iraei, Shaloo Rakheja, Sou-Chi Chang, Sou-Chi Chang, Dmitri E. Nikonov, Ian A. Young, Azad Naeemi

Circuit Simulation of Magnetization Dynamics and Spin Transport

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Rouhollah Mousavi Iraei, Phillip Bonhomme, Nickvash Kani, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Azad Naeemi

Impact of dimensional scaling and size effects on beyond CMOS All-Spin Logic interconnects

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Ahmet Ceyhan, Moongon Jung, Shreepad Panth, Sung Kyu Lim, Azad Naeemi

Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts

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Chenyun Pan, Saibal Mukhopadhyay, Azad Naeemi

An analytical approach to system-level variation analysis and optimization for multi-core processor

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Chenyun Pan, Azad Naeemi

A Proposal for a Novel Hybrid Interconnect Technology for the End of Roadmap

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Sou-Chi Chang, Ahmet Ceyhan, Vachan Kumar, Azad Naeemi

Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits

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Nickvash Kani, Azad Naeemi

Pipeline design in spintronic circuits

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2013 Ahmet Ceyhan, Azad Naeemi

Cu/Low-$k$ Interconnect Technology Design and Benchmarking for Future Technology Nodes

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Papers authored by Azad Naeemi