Kitae Lee
0000-0002-8294-5272
11 papers found
Refreshing results…
Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application
Spiking Neural Network With Weight-Sharing Synaptic Array for Multi-input Processing
Novel Dual Liner Process for Side-Shielded Forksheet Device With Superior Design Margin
Investigation of Device Performance for Fin Angle Optimization in FinFET and Gate-All-Around FETs for 3 nm-Node and Beyond
Comprehensive TCAD-Based Validation of Interface Trap-Assisted Ferroelectric Polarization in Ferroelectric-Gate Field-Effect Transistor Memory
Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap
Incremental Drain-Voltage-Ramping Training Method for Ferroelectric Field-Effect Transistor Synaptic Devices
Suppression of Statistical Variability in Stacked Nanosheet Using Floating Fin Structure
Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Processing in Memory
Negative Capacitance Effect on MOS Structure: Influence of Electric Field Variation
Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs
Missing publications? Search for publications with a matching author name.