Takafumi Fukushima
0000-0003-2303-8178
Tohoku University
198 papers found
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Intra- and inter-chip electrical interconnection formed by directed self assembly of nanocomposite containing diblock copolymer and nanometal
Study of Al-doped ZnO Transparent Stimulus Electrode for Fully Implantable Retinal Prosthesis with Three-dimensionally Stacked Retinal Prosthesis Chip
Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration
Experimental evaluation of stimulus current generator with Laplacian edge-enhancement for 3-D stacked retinal prosthesis chip
Ultrawide range square wave impedance analysis circuit with ultra-slow ring-oscillator using gate-induced drain-leakage current
3-D Sidewall Interconnect Formation Climbing Over Self-Assembled KGDs for Large-Area Heterogeneous Integration
Heterogeneous Integration at Fine Pitch (≤ 10 µm) Using Thermal Compression Bonding
Feasibility study on ultrafine-pitch Cu-Cu bonding using directed self-assembly (DSA)
Temporary Bonding and De-Bonding for Multichip-to-Wafer 3D Integration Process Using Spin-on Glass and Hydrogenated Amorphous Si
Remarkable Suppression of Local Stress in 3D IC by Manganese Nitride-Based Filler with Large Negative CTE
Minimized hysteresis and low parasitic capacitance TSV with PBO (polybenzoxazole) liner to achieve ultra-high-speed data transmission
“FlexTrate ^TM” — Scaled Heterogeneous Integration on Flexible Biocompatible Substrates Using FOWLP
Improving the barrier ability of Ti in Cu through-silicon vias through vacuum annealing
Evaluation of insertion characteristics of less invasive Si optoneural probe with embedded optical fiber
Development of Si neural probe with piezoresistive force sensor for minimally invasive and precise monitoring of insertion forces
Heterogeneous integration with high-performance and scalable substrates: Si-IF (Silicon Interconnect Fabric) and FlexTrate™
New concept of TSV formation methodology using Directed Self-Assembly (DSA)
Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology
Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications
Drastic reduction of keep-out-zone in 3D-IC by local stress suppression with negative-CTE filler
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