Takafumi Fukushima

Papers authored by Takafumi Fukushima

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2012 M. Mariappan, H. Kobayashi, T. Fukushima

, T. Tanaka, M. Koyanagi

High density Cu-TSVs and reliability issues

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Mariappan Murugesan, Hideto Hashiguchi, Harufumi Kobayashi, Takafumi Fukushima

, Tetsu Tanaka, Mitsumasa Koyanagi

W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress

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Yuki Ohara, Kang Wook Lee, Koji Kiyoyama, Shigehide Konno, Yutaka Sato, Shuichi Watanabe, Atsushi Yabata, Harufumi Kobayashi, Tadashi Kamada, Jichel Bea, Mariappan Murugesan, Hiroyuki Hashimoto, Takafumi Fukushima

, Tetsu Tanaka, Mitsumasa Koyanagi

Chip-based hetero-integration technology for high-performance 3D stacked image sensor

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K.-W. Lee, Y. Ohara, K. Kiyoyama, S. Konno, Y. Sato, S. Watanabe, A. Yabata, T. Kamada, J.-C. Bea, H. Hashimoto, M. Murugesan, T. Fukushima

, T. Tanaka, M. Koyanagi

Characterization of Chip-level Hetero-Integration Technology for High-Speed, Highly Parallel 3D-Stacked Image Processing System

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M. Murugesan, H. Kobayashi, H. Shimamoto, F. Yamada, T. Fukushima

, J. C. Bea, K. W. Lee, T. Tanaka, M. Koyanagi

Minimizing the Local Deformation Induced around Cu-TSVs and CuSn/InAu-Microbumps in High-Density 3D-LSIs

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This paper was not found in any repository, but could be made available legally by the author.

K. Kiyoyama, K.-W. Lee, T. Fukushima

, H. Naganuma, H. Kobayashi, T. Tanaka, M. Koyanagi

A very low area ADC for 3-D stacked CMOS image processing system

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K. Hozawa, F. Furuta, Y. Hanaoka, M. Aoki, K. Takeda, K. Sakuma, Kang Wook Lee, T. Fukushima

, M. Koyanagi

Chip-level TSV integration for rapid prototyping of 3D system LSIs

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2011 M. Murugesan, H. Kino, A. Hashiguchi, C. Miyazaki, H. Shimamoto, H. Kobayashi, T. Fukushima

, T. Tanaka, M. Koyanagi

High density 3D LSI technology using W/Cu hybrid TSVs

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Takafumi Fukushima

, M. Takafumi Fukushima, Eiji Iwata, Yuki Ohara, Mariappan Murugesan, Jichoel Bea, Kangwook Lee, Tetsu Tanaka, J. Murugesan, Mitsumasa Koyanagi, K. Bea, M. Lee

Multichip Self-Assembly Technology for Advanced Die-to-Wafer 3-D Integration to Precisely Align Known Good Dies in Batch Processing

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Kangwook Lee, Takafumi Fukushima

, Tetsu Tanaka, Mitsumasa Koyanagi

3D integration technology and reliability challenges

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Jichel Bea, Kangwook Lee, Takafumi Fukushima

, Tetsu Tanaka, Mitsumasa Koyanagi

Evaluation of Cu Diffusion From Cu Through-Silicon Via (TSV) in Three-Dimensional LSI by Transient Capacitance Measurement

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T. Fukushima

, Y. Ohara, M. Murugesan, J.-C. Bea, K.-W. Lee, T. Tanaka, M. Koyanagi

Self-assembly technologies with high-precision chip alignment and fine-pitch microbump bonding for advanced die-to-wafer 3D integration

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Yanli Pei, Chengkuan Yin, Toshiya Kojima, Ji-Cheol Bea, Hisashi Kino, Takafumi Fukushima

, Tetsu Tanaka, Mitsumasa Koyanagi

MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and $\hbox{HfO}_{\bf 2}$ High-k Blocking Dielectric

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Kang-Wook Lee, Akihiro Noriki, Kouji Kiyoyama, Takafumi Fukushima

, Tetsu Tanaka, Mitsumasa Koyanagi

Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems

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This paper is made freely available by the publisher.

Takafumi Fukushima

, Kojima Toshiya, Tanaka Tetsu, Eiji Iwata, Takayuki Konno, Risato Kobayashi, Mariappan Murugesan, Ji-Chel Bea, Kang-Wook Lee, Mitsumasa Koyanagi

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

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Yan Li Pei, Tatsuro Hiraki, Toshiya Kojima, Takafumi Fukushima

, Mitsumasa Koyanagi, Tetsu Tanaka

Energy Band Engineering of Metal Nanodots for High Performance Nonvolatile Memory Application

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K.-W. Lee, J.-C. Bea, T. Fukushima

, T. Tanaka, M. Koyanagi

Cu Retardation Performance of Extrinsic Gettering Layers in Thinned Wafers Evaluated by Transient Capacitance Measurement

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Jichel Bea, Kangwook Lee, Takafumi Fukushima

, Tetsu Tanaka, Mitsumasa Koyanagi

Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient-Capacitance Measurement

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This paper was not found in any repository; the policy of its publisher is unknown or unclear.

T. Tanaka, J. Bea, M. Murugesan, K. Lee, T. Fukushima

, M. Koyanagi

3D LSI technology and reliability issues

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2010 K.-W. Lee, J.-C. Bea, T. Fukushima

, T. Tanaka, M. Koyanagi

Electrical evaluation of Cu contamination behavior at the backside surface of a thinned wafer by transient capacitance measurement

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Papers authored by Takafumi Fukushima