Jong-Ho Lee
0000-0003-3559-9802
53 papers found
Refreshing results…
Optimizing Post-Metal Annealing Temperature Considering Different Resistive Switching Mechanisms in Ferroelectric Tunnel Junction
Unveiling Resistance Switching Mechanisms in Undoped HfOx Ferroelectric Tunnel Junction Using Low-Frequency Noise Spectroscopy
Effect of Carrier Transport Process on Tunneling Electroresistance in Ferroelectric Tunnel Junction
Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application
Spiking Neural Network With Weight-Sharing Synaptic Array for Multi-input Processing
Analog synaptic devices applied to spiking neural networks for reinforcement learning applications
Novel Dual Liner Process for Side-Shielded Forksheet Device With Superior Design Margin
Damage-Induced Ferroelectricity in HfOx-Based Thin Film
Capacitor-Based Synaptic Devices for Hardware Spiking Neural Networks
Investigation of Device Performance for Fin Angle Optimization in FinFET and Gate-All-Around FETs for 3 nm-Node and Beyond
Comprehensive TCAD-Based Validation of Interface Trap-Assisted Ferroelectric Polarization in Ferroelectric-Gate Field-Effect Transistor Memory
Impact of interlayer insulator formation methods on HfOx ferroelectricity in the metal–ferroelectric–insulator–semiconductor stack
Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap
Suppression of Statistical Variability in Stacked Nanosheet Using Floating Fin Structure
Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Processing in Memory
Interlayer engineering for enhanced ferroelectric tunnel junction operations in HfO x -based metal-ferroelectric-insulator-semiconductor stack
A novel physical unclonable function (PUF) using 16 × 16 pure-HfO x ferroelectric tunnel junction array for security applications
Gas sensing materials roadmap
Optimization of post-deposition annealing temperature for improved signal-to-noise ratio in In2O3 gas sensor
Suppression of reverse drain induced barrier lowering in negative capacitance FDSOI field effect transistor using oxide charge trapping layer
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