The high electron mobility of compound semiconductor materials can result in high velocity and low backscatter electrons being injected at the source side of a III-V nMOSFET. In combination, these factors have the potential to meet the highly challenging performance metrics of the International Technology Roadmap for Semiconductors (ITRS) [1] beyond the 15 nm technology generation, in particular the need to reduce supply voltages towards 0.5 V. This paper highlights a number of the significant challenges which have to be addressed if III-V MOSFETs are to be a credible solution to enable continued scaling of the ITRS beyond 2018. INTRODUCTION In recent years, the major driver in the mainstream semiconductor industry has become density scaling. This is well captured by the MOSFET gate pitch metric (a measure of the total size of a MOSFET, shown schematically in Figure 1) which, as shown in Table 1, is required to shrink through 30 nm in 2018, with a target of 15 nm by 2024.