Milos Krstic - Dissemin

Papers authored by Milos Krstic

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2019 C. Robin, S. Rochette, S. Desgrez, J. L. Muraro, D. Langrez, J. L. Roux, M. Krstic

Reliability evaluation of a 0.25 μm SiGe technology for space applications

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Z. Stamenkovic, K. Tittelbach-Helmrich, M. Krstic

, M. Stojcev, B. Dimitrijevic

Hardware/Software Co-Design of Wireless LAN Transceiver: A Case Study

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Mitko Veleski, Rolf Kraemer, Milos Krstic

SWIELD: An In Situ Approach for Adaptive Low Power and Error-Resilient Operation

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Junchao Chen, Marko Andjelkovic, Aleksandar Simevski, Yuanqing Li, Patryk Skoncej, Milos Krstic

Design of SRAM-Based Low-Cost SEU Monitor for Self-Adaptive Multiprocessing Systems

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Oliver Schrape, Anselm Breitenreiter, Steffen Zeidler, Milos Krstic

Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops

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Anselm Breitenreiter, Jesus Lopez, Pedro Reviriego, Milos Krstic

, Ursula Gutierro, Manuel Sanchez-Renedo, Daniel Gonzalez

A Radiation Tolerant 10/100 Ethernet Transceiver for Space Applications

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Marko Andjelkovic, Yuanqing Li, Zoran Stamenkovic, Milos Krstic

, Rolf Kraemer

Characterization and Modeling of SET Generation Effects in CMOS Standard Logic Cells

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Aleksandar Simevski, Milos Krstic

Simulation-based Verification of the Youngest-First Round-Robin Core Gating Pattern

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Anselm Breitenreiter, Stefan Weidling, Oliver Schrape, Steffen Zeidler, Pedro Reviriego, Milos Krstic

Selective Fault Tolerance by Counting Gates with Controlling Value

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Emilio Arnieri, Luigi Boccia, Giandomenico Amendola, Srdjan Glisic, Chunxu Mao, Steven Gao, Tobias Rommel, Piotr Penkala, Milos Krstic

, Uroschanit Yodprasit, U. Yodprasity, Anselm Ho, Oliver Schrape, Marwan Younis

Highly Integrated Dual-Band Dual-Polarized Antenna Tile for SAR Applications

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2018 Marko Andjelkovic, Milan Babic, Yuanqing Li, Oliver Schrape, Milos Krstic

, Rolf Kraemer

Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates

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Mahdi Tala, Oliver Schrape, Milos Krstic

, Davide Bertozzi

Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip

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Oliver Schrape, Alexey Balashov, Aleksandar Simevski, Carlos Benito, Milos Krstic

Master-Clone Placement with Individual Clock Tree Implementation – a Case on Physical Chip Design

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Marko Andjelkovic, Zoran Stamenkovic, Milos Krstic

, Rolf Kraemer

Impact of Resistive Open and Bridge Defects on the SET Robustness of Standard CMOS Combinational Logic

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Milos Krstic

, Anne-Kristin Jentzsch

Reliability Safety and Security of the Electronics in Automated Driving Vehicles – Joint Lab Lecturing Approach

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Yuanqing Li, Li Chen, Issam Nofal, Mo Chen, Haibin Wang

, Rui Liu, Qingyu Chen, Milos Krstic

, Shuting Shi, Gang Guo, Sang H. Baeg, Shi-Jie Wen, Richard Wong

Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree

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Oliver Schrape, Anselm Breitenreiter, Marko Andjelkovic, Milos Krstic

D-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-Flop

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Milos Krstic

, Aleksandar Simevski, Markus Ulbricht, Stefan Weidling

Power/Area-Optimized Fault Tolerance for Safety Critical Applications

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Mahdi Tala, Oliver Schrape, Milos Krstic

, Davide Bertozzi

Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges

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Papers authored by Milos Krstic