Bharat Bhuva
0000-0002-2171-100X
Vanderbilt University
15 papers found
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Measured Energy-Dependent Neutron Attenuation through the Stacked Printed Circuit Boards
SE Response of Guard-Gate FF in 16-nm and 7-nm Bulk FinFET Technologies
Empirical Modeling of FinFET SEU Cross Sections Across Supply Voltage
Effects of Total-Ionizing-Dose Irradiation on Single-Event Response for Flip-Flop Designs at a 14-/16-nm Bulk FinFET Technology Node
Power-Aware SE Analysis of Different FF Designs at the 14-/16-nm Bulk FinFET CMOS Technology Node
Dual-Interlocked Logic for Single-Event Transient Mitigation
Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation
Analysis of Temporal Masking Effects on Master- and Slave-Type Flip-Flop SEUs and Related Applications
Atmospheric-Like Neutron Attenuation During Accelerated Neutron Testing With Multiple Printed Circuit Boards
Frequency Dependence of Heavy-Ion-Induced Single-Event Responses of Flip-Flops in a 16-nm Bulk FinFET Technology
Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques
The Impact of Charge Collection Volume and Parasitic Capacitance on SEUs in SOI- and Bulk-FinFET D Flip-Flops
Time-Domain Modeling of All-Digital PLLs to Single-Event Upset Perturbations
Exploiting Parallelism and Heterogeneity in a Radiation Effects Test Vehicle for Efficient Single-Event Characterization of Nanoscale Circuits
An Empirical Model for Predicting SE Cross Section for Combinational Logic Circuits in Advanced Technologies
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