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Verifying SystemC using stateful symbolic simulation
Download from citeseerx.ist.psu.eduAutomated and quality-driven requirements engineering
Download from citeseerx.ist.psu.eduExact Routing for Digital Microfluidic Biochips with Temporary Blockages
Download from www.researchgate.netAutomatic refinement checking for formal system models
Download from citeseerx.ist.psu.eduVerifying consistency between activity diagrams and their corresponding OCL contracts
Download from citeseerx.ist.psu.eduMetaSMT: a unified interface to SMT-LIB2
Download from citeseerx.ist.psu.eduAncilla-free synthesis of large reversible functions using binary decision diagrams
Download from www.researchgate.netEmbedding of Large Boolean Functions for Reversible Logic
Download from arxiv.orgGenerating SystemC Implementations for Clock Constraints Specified in UML/MARTE CCSL
Download from citeseerx.ist.psu.eduImproving Coverage of Simulation-Based Verification by Dedicated Stimuli Generation
Download from citeseerx.ist.psu.eduIncorporating user preferences in many-objective optimization using relation ε-preferred
Download from citeseerx.ist.psu.eduUpper bounds for reversible circuits based on Young subgroups
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