Yongpan Liu
0000-0002-4892-2309
41 papers found
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Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm CMOS
Modification of Indium Tin Oxide Electrodes by Fluorinated Silanes for Transparent Organic Thin-Film Transistors
ULSeq-TA: Ultra-Long Sequence Attention Fusion Transformer Accelerator Supporting Grouped Sparse Softmax and Dual-Path Sparse LayerNorm
A Module-Level Configuration Methodology for Programmable Camouflaged Logic
TFT-Based Near-Sensor In-Memory Computing: Circuits and Architecture Perspectives of Large-Area eDRAM and ROM CiM Chips
GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility
A Heterogeneous Microprocessor for Intermittent AI Inference using Nonvolatile-SRAM-based Compute-In-Memory
A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching
RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel
Low-Power and Scalable BEOL-Compatible IGZO TFT eDRAM-Based Charge-Domain Computing
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration
SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree
FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations
Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution
An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree
A Low-Temperature Poly-Silicon Thin Film Transistor Pixel Circuit for Active-Matrix Simultaneous Neurostimulation
FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge
A Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference
Reliable and Efficient Parallel Checkpointing Framework for Nonvolatile Processor With Concurrent Peripherals
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