Vishesh Dokania
0000-0003-0000-3052
Intel Corporation
3 papers found
Refreshing results…
Analytical Modeling of Wrap-Gate Carbon Nanotube FET With Parasitic Capacitances and Density of States
Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells
Design of variation-resilient CNFET-based Schmitt trigger circuits with optimum hysteresis at 16-nm technology node
Missing publications? Search for publications with a matching author name.