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Proceedings of the 30th Symposium on Integrated Circuits and Systems Design Chip on the Sands - SBCCI '17

DOI: 10.1145/3109984.3109985

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Latency reduction of fault-tolerant NoCs by employing multiple paths

Proceedings article published in 2017 by Ronaldo T. P. Milfont, Rafael G. Mota, João M. Ferreira, Paulo C. Cortez, César Marcon ORCID, Daniel A. B. Tavares, Jarbas A. N. Silveira
This paper was not found in any repository; the policy of its publisher is unknown or unclear.
This paper was not found in any repository; the policy of its publisher is unknown or unclear.

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