Impact of strain on access resistance in planar and nanowire CMOS devices

Berthelon, R.; Andneu, F.; Triozon, F.; Casse, M.; Bourdet, L.; Ghibaudo, G.; Rideau, D.; Niquet, Y. M.; Barraud, S.; Nguyen, P.; Le Royer, C.; Lacord, J.; Tabone, C.; Rozeau, O.; Dutartre, D.; Claverie, A.; Josse, E.; Andrieu, F.; Arnaud, F.; Vinet, M.

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2017 Symposium on VLSI Technology

DOI: 10.23919/vlsit.2017.7998180

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Impact of strain on access resistance in planar and nanowire CMOS devices

Proceedings article published in 2017 by R. Berthelon, F. Andneu, F. Triozon, M. Casse, L. Bourdet, G. Ghibaudo, D. Rideau, Y. M. Niquet, S. Barraud, P. Nguyen, C. Le Royer, J. Lacord, C. Tabone, O. Rozeau, D. Dutartre and other authors.

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Impact of strain on access resistance in planar and nanowire CMOS devices