Published in
2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO)
DOI: 10.1109/nano.2016.7751500
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Design and simulation of steep-slope silicon-on-insulator FETs using negative capacitance: Impact of buried oxide thickness and remnant polarization
Proceedings article published in 2016 by
Hiroyuki Ota,
Shinji Migita,
Junichi Hattori,
Koichi Fukuda 
,
Akira Toriumi,
Ieee
,
Akira Toriumi,
Ieee
