Published in

2016 14th IEEE International New Circuits and Systems Conference (NEWCAS)

DOI: 10.1109/newcas.2016.7604803

Links

Tools

Export citation

Search in Google Scholar

Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generator

Proceedings article published in 2016 by Yun-Nan Chang
This paper was not found in any repository; the policy of its publisher is unknown or unclear.
This paper was not found in any repository; the policy of its publisher is unknown or unclear.

Full text: Unavailable

Question mark in circle
Preprint: policy unknown
Upload
Question mark in circle
Postprint: policy unknown
Upload
Question mark in circle
Published version: policy unknown
Upload