引入半導體產業最重要的摩爾定律做為引子後，簡述半導體製造在各節點技術演進上，碰上對應的製程技術挑戰與如何克服之過程，以及藉由現今研究之趨勢，對未來10奈米以下節點技術發展做預測，同時簡單介紹何為短通道及窄通道效應。 本論文第一部分簡述三五族材料特性、高載子遷移率電晶體之發展歷史與現況，並提出鰭狀結構之高載子遷移率電晶體，透過TCAD進行模擬，並由模擬結果建立其閘極控制機制之理論，同時透過製程實作出元件並進行量測分析，可成功的以該理論解釋量測分析之結果。 第二部分簡述鐵電材料之材料特性，並以電路學與能量兩個不同角度切入解釋負電容之成因，透過製程實作出電容元件，並進行量測與分析，探討鐵電材料於不同結晶溫度下，在不同頻率下的電容電壓特性及漏電流特性，同時以電導法分析其介面特性，探討不同退火溫度對介面特性之影響。 第三部分簡述鐵電材料應用於電晶體之發展與其優缺點，以製程實作出元件，同時進行量測與分析，探討不同退火溫度對元件特性造成之影響，並以TCAD模擬，探討不同模擬條件下之元件特性，作為未來的改進方向。 ; After describing Moore’s Law, we introduce node technology progression of semiconductor manufacturing in this thesis, including the corresponding challenges and the solution to them. After studying research trends, we predict sub-10nm node technology development, and introduce short-channel effects (SCEs) and narrow-channel effects (NCEs) briefly. In the first part, we introduce III-V material characteristics, and their developing history and operating principles of high electron mobility transistors (HEMTs). We propose fin structures of HEMTs, and use TCAD to simulate. From simulation results, the theory of gate control mechanisms is proposed. We fabricate and measure the device, the measurement results can be explained by the proposed theory successfully. In the second part, we introduce ferroelectric material to form negative capacitance (NC), and use two different viewpoints of circuit and energy to explain it. We fabricate MOS capacitances and discuss their C-V, I-V, and interface characteristics at different crystalline temperatures and frequencies. In the third part, we introduce development, pros and cons of negative capacitance field effect transistors (NCFETs). We fabricate and discuss their I-V characteristics in different crystalline temperatures. Finally, we use TCAD to simulate different conditions of NCHEMTs, and the results are regarded as improving ways in the future. ; 光電工程學研究所 ; 電機資訊學院 ; 博碩士論文