Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.
DOI: 10.1109/iscas.2003.1206110
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電機工程學系 ; In this paper, we propose efficient techniques and architectures for realizing spatial-downscaling transcoders in the DCT domain. We also present methods for re-sampling motion vectors and determining coding modes. We propose a novel drift-free architecture which simplifies the cascaded DCT-domain downscaling transcoder (CDDT) by integrating the downscaling process into the DCT-domain motion compensation (DCT-MC) operation for B frames, thus reducing the computation for DCT-MC and downscaling. We also propose another scheme to further reduce the computation which may introduce drift errors. Experimental results show that the two proposed schemes can achieve significant computation reduction compared with the original CDDT without any degradation or with introducing acceptable quality degradation, respectively.