Semiconductor packaging technology requires understanding how the fundamental materials properties of different structures interact to impact the final reliability of the system, how to measure those properties and how to control them. We investigated the impact of residual stress of electrodeposited Ni (sulfamate) and Cu (sulfate and MSA) deposits that are used for C4 (controlled collapse chip connection) interconnects using X-ray lattice distortion method, sin2ψ and wafer bow measurement as a function of thermal excursions up to 400 C. The impact of this stress on the final reliability of a flip chip package was studied in order to determine useful guidelines to limit post-plate process temperatures, to conduct anneals when possible, to establish best known methods to monitor plated materials stresses and to develop methods to maintain and condition chemical plating baths to control those deposits. Finally, dynamic SIMS was utilized to aid in the interpretation of those data.