Published in
2014 Symposium on VLSI Circuits Digest of Technical Papers
DOI: 10.1109/vlsic.2014.6858446
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A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement
Proceedings article published in 2014 by
Romesh Kumar Nandwana,
Tejasvi Anand,
Saurabh Saxena,
Seong-Joong Kim,
Mrunmay Talegaonkar,
Ahmed Elkholy,
Woo-Seok Choi,
Amr Elshazly,
Pavan Kumar Hanumolu
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