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2012 IEEE International Interconnect Technology Conference

DOI: 10.1109/iitc.2012.6251646

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Compact modeling and performance optimization of 3D chip-to-chip interconnects with transmission lines, vias and discontinuities

This paper was not found in any repository, but could be made available legally by the author.
This paper was not found in any repository, but could be made available legally by the author.

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