High performance and low power transistors integrated in 65nm bulk CMOS technology

Luo, Z.; Steegen, A.; Eller, M.; Mann, R.; Baiocco, C.; Nguyen, P.; Kim, L.; Hoinkis, M.; Ku, V.; Klee, V.; Jamin, F.; Wrschka, P.; Shafer, P.; Lin, W.; Fang, S.; Ajmera, A.; Tan, W.; Park, D.; Mo, R.; Lian, J.; Vietzke, D.; Coppock, C.; Vayshenker, A.; Hook, T.; Chan, V.; Kim, K.; Cowley, A.; Kim, S.; Kaltalioglu, E.; Ku, J.; Zhang, B.; Marokke, S.; Marokkey, S.; Lin, Y.; Lee, K.; Zhu, H.; Weybright, M.; Rengarajan, R.; Schim, T.; Schiml, T.; Sudijono, J.; Yang, I.; Yang, J.; Wann, C.

Published in

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.

DOI: 10.1109/iedm.2004.1419254

Tools

Export citation

Search in Google Scholar

High performance and low power transistors integrated in 65nm bulk CMOS technology

Proceedings article published in 2005 by Z. Luo, A. Steegen, M. Eller, R. Mann, C. Baiocco, P. Nguyen, L. Kim, M. Hoinkis, V. Ku, V. Klee, F. Jamin, P. Wrschka, P. Shafer

, W. Lin, S. Fang and other authors.

This paper was not found in any repository, but could be made available legally by the author.

Full text: Unavailable

Preprint: archiving allowed

Upload

Postprint: archiving allowed

Upload

Published version: archiving forbidden

Policy details

Data provided by

Published in

Links

Tools

High performance and low power transistors integrated in 65nm bulk CMOS technology