We present the experimental analysis of planar Si p-tunnel FETs (TFETs) fabricated on ultrathin body Silicon on Insulator (SOI) substrates by an optimized dopant implantation into silicide process. The average subthreshold swing of such planar TFETs reaches 75 mV/decade over four orders of magnitude of drain current. Emphasis is placed on the capacitance- voltage analysis of TFETs. In contrast to simulation predictions, we provide experimental evidence that the contribution of Cgs to the total gate capacitance increases at on-state, which in turn results in a decrease of the gate-to-drain capacitance Cgd. This beneficial effect could result in a reduction of the Miller capacitance effect in TFETs-based circuits.