This work implements and evaluates the recent complete addition formulae for the prime order elliptic curves of Renes, Costello and Batina on an FPGA platform. We implement three different versions: (1) an unprotected architecture; (2) an architecture protected through coordinate randomization; and (3) an architecture with both coordinate randomization and scalar splitting in place. The evaluation is done through timing analysis and test vector leakage assessment (TVLA). Theresultsshowthatapplyinganincreasinglevelofcountermeasuresleadstoanincreasingresistance against side-channel attacks. This is the first work looking into side-channel security issues of hardware implementations of the complete formulae.