Reduced Instruction Set Computers (RISC) have received much attention in the last few years. The RISC design philosophy has led to a profound re-evaluation of long held. Yet the precise definition of what "RISC design" really means, is something which has been obscured by the unfounded claims of some microprocessor manufacturers and by the reductionist definitions found in the popular computer literature. In this paper we define RISC in a hierarchical manner focusing the analysis on the essential features of this new architectural paradigm. Several RISC architectures are discussed and the relevant data is summarized with the help of graphs. The closing section discusses future possible developments in the field of computer architecture.