Published in
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)
DOI: 10.1109/vlsit.2001.934932
Links
Tools
W/WN/poly gate implementation for sub-130 nm vertical cell DRAM
Proceedings article published in 1970 by
R. Malik,
L. Clevenger,
I. McStay,
O. Gluschenkov,
W. Robl,
P. Shafer 
,
G. Stojakovic,
W. Yan,
M. Naeem,
R. Ramachandran,
K. Wong,
J. Prakash,
W. Kang,
Y. Li,
R. Vollertsen
and other authors.
,
G. Stojakovic,
W. Yan,
M. Naeem,
R. Ramachandran,
K. Wong,
J. Prakash,
W. Kang,
Y. Li,
R. Vollertsen
and other authors.
This paper was not found in any repository, but could be made available legally by the author.
Full text: Unavailable
Published version:
archiving forbidden
Data provided by 