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2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

DOI: 10.1109/csics.2013.6659233

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Improved GaN-on-SiC Transistor Thermal Resistance by Systematic Nucleation Layer Growth Optimization

Journal article published in 2013 by J. Pomeroy, Niklas Rorsman ORCID, Jr-Tai Chen, U. Forsberg, E. Janzen, M. Kuball
This paper was not found in any repository, but could be made available legally by the author.
This paper was not found in any repository, but could be made available legally by the author.

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Abstract

Impressive power densities have been demonstrated for GaN-on-SiC based high-power high-frequency transistors, although further gains can be achieved by further minimizing the device thermal resistance. A significant 10-30% contribution to the total device thermal resistance originates from the high defect density AlN nucleation layer at the GaN/SiC interface. This thermal resistance contribution was successfully reduced by performing systematic growth optimization, investigating growth parameters including: Substrate pretreatment temperature, growth temperature and deposition time. Interfacial thermal resistance, characterized by time resolved Raman thermography measurements AlGaN/GaN HEMT structures, were minimized by using a substrate pretreatment and growth temperature of 1200 °C. Reducing the AlN thickness from 105 nm (3.3×10-8 W/m2K) to 35 nm (3.3×10-8 W/m2K), led to a ~2.5× interfacial thermal resistance reduction and the lowest value reported for a standard AlGaN/GaN HEMT structure.