Several solutions for implementing Petri net models on FPGA thanks to a transformation in a VHDL code have been proposed in literature. But none deals with the manage- ment of transition conflicts in the specific case of synchronous implementation of interpreted Petri nets. This article presents an automatic method to deal with conflicts from their detection to their implementation on FPGA. One solution for binary Petri nets is proposed. For the generalized case, two solutions are proposed and experimentally compared. Thus a solution is provided for the implementation of interpreted generalized time Petri nets.