Published in
Sixteenth International Symposium on Quality Electronic Design
DOI: 10.1109/isqed.2015.7085495
Links
Tools
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node
Proceedings article published in 2015 by
Chenyun Pan,
Praveen Raghavan,
Francky Catthoor,
Zsolt Tokei,
Azad Naeemi 
This paper was not found in any repository, but could be made available legally by the author.
Full text: Unavailable
Published version:
archiving forbidden
Data provided by 