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2015 IEEE International Symposium on Circuits and Systems (ISCAS)

DOI: 10.1109/iscas.2015.7168617

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Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS

Proceedings article published in 2015 by Prakash Harikumar, J. Jacob Wikner ORCID
This paper was not found in any repository, but could be made available legally by the author.
This paper was not found in any repository, but could be made available legally by the author.

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