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Elsevier, Microelectronic Engineering, 3(87), p. 421-425

DOI: 10.1016/j.mee.2009.07.002

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Characterization and impact of reduced copper plating overburden on 45nm interconnect performances

This paper was not found in any repository, but could be made available legally by the author.
This paper was not found in any repository, but could be made available legally by the author.

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Abstract

During first metal level interconnects fabrication, a controlled modification of the electro-deposited copper over-deposition (overburden) is performed using a partial chemical–mechanical polishing (CMP) step. Next, copper microstructure is stabilized with a short duration hot-plate anneal. Overburden is then removed during CMP end-of-step. Ionic microscopy and EBSD observations of overburden thickness reduction reveal that copper grain growth occurs differently, according to patterned geometries and with a strong (1 1 1) texture, as observed in modified films. Reduction of overburden thickness also reveals the capacity of anneal temperature to impact electrical performances. Reliability is impacted for thinnest wires.