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Trans Tech Publications, Materials Science Forum, (806), p. 143-147, 2014

DOI: 10.4028/www.scientific.net/msf.806.143

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Probing at Nanoscale Underneath the Gate Oxides in 4H-SiC MOS-Based Devices Annealed in N<sub>2</sub>O and POCl<sub>3</sub>

This paper was not found in any repository, but could be made available legally by the author.
This paper was not found in any repository, but could be made available legally by the author.

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Abstract

In this paper a comparative study of the impact of N2O and POCl3 annealing on the SiO2/SiC system is presented, combining nanoscale electrical characterization of SiC surface doping by scanning spreading resistance microscopy (SSRM) and scanning capacitance microscopy (SCM) to the conventional capacitance-voltage (C-V) and current-voltage (I-V) measurements on MOS-based devices. A significant reduction of the interface states density (from 1.8×1012 to 5.7×1011 cm-2eV-1) and, correspondingly, an increase in the carrier mobility (from 19 to 108 cm2V-1s-1) was found moving from N2O to POCl3 annealing. Furthermore, SSRM measurements on bare p+-type SiC regions selectively exposed to N2O and POCl3 at high temperature provided the direct demonstration of the incorporation of N or P-related donors in the SiC surface, leading to a partial compensation of substrate acceptors during N2O treatment and to an overcompensation during POCl3 annealing. Finally, cross-sectional SCM profiles performed on epitaxial n-doped 4H-SiC with 45 nm SiO2 (subjected to post deposition annealing in the two ambients) allowed to quantify the active donors concentrations associated to P or N incorporation under the gate oxide, showing almost a factor of ten higher doping (4.5×1018cm-3 vs 5×1017cm-3) in the case of P related donors.