This work describes test structures and modeling which have been applied to characterize SET pulse widths of standard ATMEL CMOS libraries in 180 and 90-nm technologies. The modeling methodology from physical-level to electrical-level induced SEU/MBU and SET, is also presented. The methodology includes the GDS extractor, the physical (carrier generation, transport and charge collection) and the circuit levels. The devices and test vehicles characterized in this work range from inverter to fully functional SRAMs integrating standard and hardened circuits. Then, this work analyses SET measured on test structures including circuits designed and fabricated in 180-nm and 90-nm processes. Results obtained for a 180-nm SRAM cell and a DFF are consistent. For the 90-nm cells, results obtained are less satisfactory. Nevertheless, the comparisons between the experiment and the calculation about the impact induced by the drive strength or the load configuration are consistent. Results issued from complex cell (i.e. customized DFF) show that modeling is relevant for designing efficient hardening cells for aerospace applications. Indeed, the SET or SEU sensitivity maps, the cross sections, and the SET distributions give precious information to the radiation expert designer about the efficiency and reliability of the chosen hardened techniques.