The origins of gate-induced hysteresis in carbon nanotube field-effect transistors are explained and techniques to eliminate this hysteresis with encapsulating layers of methylsiloxane and modified processes for nanotube growth are reported. A combined experimental and theoretical analysis of the dependence of hysteresis on the gate voltage sweep-rate reveals the locations, types, and densities of defects that contribute to hysteresis. Devices with designs that eliminate these defects exhibit more than ten times reduction in hysteresis compared to conventional layouts. Demonstrations in individual transistors that use both networks and arrays of nanotubes, and in simple logic gates built with these devices, illustrate the utility of the proposed approaches.