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2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

DOI: 10.1109/iscas.2002.1010224

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A micropower log domain FGMOS filter

Proceedings article published in 2002 by E. O. Rodriguez Villegas, A. Rueda, A. Yufera ORCID
This paper is available in a repository.
This paper is available in a repository.

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Abstract

In this paper, a CMOS implementation of a low voltage micropower logarithmic biquad based on floating gate MOS transistors (FGMOS) is presented. The translinear principle applied to the floating gate MOS transistor leads to an easy implementation of the state-space equations without using the source terminal in the loop. The voltage supply can be reduced and also there is no need of separate wells. The technique is proven in this low/band pass filter working at 1 V with a maximum power consumption of 2 μW. The filter parameters can be adjusted in more than two decades, being the upper frequency around 150 kHz.