Exploiting the huge computing power of modern micro-processors requires fast, accurate branch predictors: as clock rates rise and pipeline lengths grow, so do branch misprediction penalties. These latencies currently repre-sent one of the largest microarchitectural performance bot-tlenecks. The literature is rich with techniques that increase accuracy, reduce prediction latencies, or both. Nonetheless, even with seemingly high prediction accuracies, branch misprediction latencies still have significant, negative per-formance effects on codes that are not memory bound. Some of the most novel recent proposals are based on the perceptron, a simple neural network component. We study of a set of perceptron-based predictors that improve predic-tion accuracies by 18.2% to 69.7%, with a mean of 37.6%. On the basis of these findings, we explore performance for a set of new perceptron-based predictors, comparing them to traditional schemes and the best perceptron-based pre-dictors published at the time of this writing. For an Alpha 21264-like architecture, the new predictors increase IPC by up to 14.14% over the 21264, and up to 9.28% over the original perceptron (with means of 5.9% and 3.67%, re-spectively). For a 20-stage pipeline, our designs improve IPCs by up to 19.35% over the original perceptron.