An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

Sakata, T.; Horiguchi, M.; Sekiguchi, T.; Ueda, S.; Tanaka, H.; Yamasaki, E.; Nakagome, Y.; Aoki, M.; Kaga, T.; Ohkura, M.; Nagai, R.; Murai, F.; Tanaka, T.; Iijima, S.; Yokoyama, N.; Gotoh, Y.; Shoji, I.; Kisu, T.; Yamashita, H.; Nishida, T.; Takeda, E.

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Institute of Electrical and Electronics Engineers, IEEE Journal of Solid-State Circuits, 11(30), p. 1165-1173, 1995

DOI: 10.1109/4.475703

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An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

Journal article published in 1995 by T. Sakata, M. Horiguchi, T. Sekiguchi, S. Ueda, H. Tanaka, E. Yamasaki, Y. Nakagome, M. Aoki, T. Kaga, M. Ohkura, R. Nagai, F. Murai, T. Tanaka, S. Iijima, N. Yokoyama and other authors.

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An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture