Silicon nanowire transistors (NWTs) are considered one of the most promising device architectures for sub 7-nm CMOS technology [1]. In such ultra-scaled devices the quantum mechanical effects are playing a significant role that determines the device performance [2]. These quantum confinement effects introduces threshold voltage shift, simultaneously reducing the gate-to-charge capacitance and the charge in the channel available for transport [3]. Hence, in order accurately to describe the device performance in such ultra-scaled transistors, calculations considering quantum mechanical effect are mandatory. In this paper, taking into account the quantum confinement effects, we establish a link between different cross-sections of two NWTs and the device performance.