The efficiency of pairing based cryptosystems depends on the computation of pairings. pairings is defined over finite fileds GF by trinomials due to efficiency. The hardware architectures for pairings have been widely studied. This paper proposes new adder and multiplier for GF(3) which are more efficient than previous results. Furthermore, this paper proposes a new unified adder-subtractor for GF based on the proposed adder and multiplier. Finally, this paper proposes new multiplier for GF. The proposed MSB-first bit-serial multiplier for GF reduces the time delay by approximately 30 % and the size of register by half than previous LSB-first multipliers. The proposed multiplier can be applied to all finite fields defined by trinomials.