System Efficient ESD Design (SEED) [1] at present requires static response data from the devices and circuitry used along the protection chain, typically from the point of entry at the PCB boundary i.e. connector up to the circuit on-chip to be protected. On this path there may be external ESD protection i.e. voltage clamping, interconnect path delay with specific transmission line properties, package design, on-chip protection design all with parasitic layout effects and ultimately the on-chip circuit(s) to be protected, being unpowered or powered. The present way of using transmission line pulse (TLP) [2-4] to obtain the response parameters is inadequate as only the averaged I/V response parameters are used after 70% of the TLP pulse width used. With most commercially available TLP testers the bandwidth used (to obtain these I/V parameters at typ. 70 ns) is also insufficient to gather the full SEED information required. For the multiple SEED applications to be implemented, dynamic response parameters are needed in time and frequency domain, as the protection device response parameters are affected by the presence of RF energy e.g. with smart phone and other wireless appliances. Furthermore, the dynamic response parameters are a function of the DC bias voltage applied i.e. devices being powered or unpowered as well as temperature. In this 1 st paper constraints and ideas are given to gather the multi-dimensional response parameters together with their rationales. At the end of the paper some examples will be presented. Future parts will contain data analysis, model building and model validation.