The trend of merging computation and wireless communications into SoCs has its reflection on the underlying circuits. Integrating multiple radios into an advanced CMOS process has the potential to reduce costs, ease platform integration and enable further area scaling over technology nodes. This is the case, however, only if the radios are designed with a completely new mindset: Focusing on “digital CMOS-friendly” implementations, robust against interference and process variation. Radio architectures have to be reconsidered to enhance their linearity, while reducing analog and RF complexity where possible. Process scaling lowers the cost of digital signal processing, which can be exploited for digitally assisted analog, Build-In-Self-Test (BIST) and calibration, leading to small, scalable, reliable and low power CMOS radios.