In recent years, continuous research efforts have been concentrating in increasing ΣΔ modulators operating frequency, while still reducing their power consumption. Indeed, when the ΣΔ modulator figure of merit (FoM) is less than 1 pJ/conversion, the decimation filter power consumption becomes a critical parameter. This paper presents a low power sin³ FIR filter for ΣΔ modulators. The proposed filter implements a decimation by 4, operating at 64 MHz and consumes only 0.1 pJ/sample processed. The circuit has been implemented and simulated in a 0.18-μm CMOS technology, showing an overall power consumption reduction of about 67% with respect to a conventional design. Finally, a silicon area reduction of 17% in the combinatory part of the filter can also be achieved.