Traditional testing methods attempt to maximize the number of single stuck-at faults detected by the test pattern set applied to minimize defective part level after IC manufacture and prior to shipment. However, stuck-at faults no longer map closely to actual defects in current CMOS technologies. This work optimizes the probability of defect detection -- in contrast to the stuck-at fault detection. I. Introduction The goal of the research was to develop a method to improve the ATPG targeting for enhanced detection of manufacturing defects in integrated circuits. Although stuck-at fault detection is widely accepted in industry as a key test quality figure of merit, it does not account for the necessity of detecting other defect types seen in real manufacturing environments. Other researchers have addressed this problem by using defect models during the ATPG process. In this case, the fault simulation engine is modified to allow the simulation of the defect models used to emulate real d...