Phase-change random access memory (PRAM) is one of the best candidates for high scale non-volatile memories due to its high programming speed, excellent endurance, and compatibility with unidirectional diode operation. However, D0 and D1 states in PRAM are produced by heat, which can induce the thermal disturbance between adjacent bits as the cell arrays continuously shrinks. Therefore, the shape of PRAM cell is changing from the conventional planar type with patterning process into the GST confined type cell, in which the reset current can be reduced dramatically and the interfaces between the cells block the heat propagation into the adjacent cell effectively. In recent, GST is confined to narrower ring type trench in order to attain much smaller reset current. PRAM has a large resistance difference between set and reset states, so the research to introduce additional 2 data states between D0 and D1 has been carried out. In order to achieve the stable 4 level multi level cell (MLC) operation and avoid overlap of two adjacent resistance level, resistance drift of amorphous phase has to be minimized. Drift is known as coming from structural distortion when melt-quenched into amorphous and its relaxation with time, so the reduction of the distortion can be the way to minimize drift of amorphous resistance and achieve the stable MLC operation. The additional 2 data states have to be written by programming algorithm because the programming windows of the additional 2 states are smaller than the D0 and D1. As reported about various write and verify algorithms, we tested falling time variation as well as amplitude variation of programming pulse. In this paper, we review the progress of cell array scaling and state of the art of MLC in PRAM, and estimate the write and verify algorithm.