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The 17th Annual SEMI/IEEE ASMC 2006 Conference

DOI: 10.1109/asmc.2006.1638790

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The Effect of Wafer Substrate Resistance on Inter Poly Oxide Thickness Variation

Proceedings article published in 1 by J. M. Towner, J. J. Naughton
This paper was not found in any repository, but could be made available legally by the author.
This paper was not found in any repository, but could be made available legally by the author.

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Abstract

In our mixed signal devices, deposited oxides are used in structures such as poly-poly capacitors. Wafers using highly doped substrates showed good thickness uniformity but uniformity deteriorated as the resistance of the substrate increased. Other factors that increased substrate resistance also increased nonuniformity. Thickness variation was correlated to electrostatic charge imparted to the wafer from poorly grounded wafer handling robotics. This charging likely caused plasma instabilities that promoted the absorption and reaction of the TEOS intermediates