A bandpass ΣΔ modulator with two time-interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40 MHz IF provide a signal band of 1 MHz with 72 dBFS DR and 65.1 dB peak SNR. The circuit, integrated in a 0.18 μm CMOS technology, uses a 60 MHz clock per channel. Experimental results show that the in-band region is not affected by tones caused by mismatches and that a two-tones input causes an 1MD signal of 68 dBc. The power consumption is 16 mW with 1.8 V supply.