— In this paper we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWT) for application in advanced CMOS technologies. The 3D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2D cross-sections along the direction of the transport are presented. The simulated NWTs have cross-sections and dimensional characteristics representative of the transistors expected at 7nm CMOS technology. Different gate lengths, cross-section shapes, spacer thicknesses and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, the mobile charge in the channel, the drain-induced barrier lowering and the sub-threshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs is also investigated. We have also estimated the optimal gate length for different NWT design conditions.