Use of atomic layer deposition (ALD) for creating well-controlled film stacks has been gaining wider acceptance in the semiconductor industry. Despite its lower throughput and higher cost-of-ownership compared to CVD, even cost-sensitive DRAM manufacturers are choosing ALD because of its ability to deal with scaling challenges such as achieving conformal coverage of high-aspect ratio features while maintaining control of high-k dielectric composition. Moreover, logic and memory producers alike find that ALD provides a level of control on interfaces, doping, and step coverage that is imperative for new-generation applications. From a process development perspective, ALD's inherently low throughput leads to long learning cycles and makes identification of optimum processes very challenging. A typical 80Å ALD film can take 3 hours/wafer in a single-wafer tool. In high-volume manufacturing, batch tools are preferred for their higher throughput, but this severely limits the exploration of ALD process space, and can lead to local optimization of baseline processes and materials. While an ALD unit process that meets composition and/or step coverage specifications is necessary, it is not sufficient for rapid and thorough development of sub-50nm IC technology. The ALD film stack still needs to be integrated into a "cell," which in turn has to meet all the device specifications. For a logic flow, this could be the effective work function of MOSCAP, while for a DRAM flow, MIMCAP leakage/K requirements must be met. With most performance improvements for logic and memory driven by new materials, many of which are deposited by ALD, there is a strong need for a flexible platform that provides fast learning cycles based on much higher throughput.