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Proceedings. 15th Symposium on Computer Architecture and High Performance Computing

DOI: 10.1109/cahpc.2003.1250319

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The Limits of Speculative Trace Reuse on Deeply Pipelined Processors

Journal article published in 2004 by Maurcio L. Pilla, A. T. da Costa, P. O. A. Navaux, Mary Lou Soffa, Amarildo T. Da Costa, Felipe M. G. Franca ORCID, Bruce R. Childers
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Abstract

Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ready by the time the reuse test is done. For these cases, we developed a new technique called Reuse through Speculation on Traces (RST), where trace inputs may be predicted. This paper studies the limits of RST for modern processors with deep pipelines, as well as the effects of constraining resources on performance. We show that our approach reuses more traces than the non-speculative trace reuse technique, with speedups of 43% over a non-speculative trace reuse and 57% when memory accesses are reused.