This paper reports a new pattern design method improving the throughput of the character projection electron beam direct writing (CP-EBDW) lithography for cell-based logic devices. The shot count decreases to approximately one fifth in a 90 nm CMOS technology by assembling the standard cells (SCs) in the physical design stage and exposing them at a time with multiple-cell shot technique. The operating frequency degradation of the logic devices is less than 5 %