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Thirteenth International Symposium on Quality Electronic Design (ISQED)

DOI: 10.1109/isqed.2012.6187504

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Device- and system-level performance modeling for graphene P-N junction logic

Proceedings article published in 2012 by Chenyun Pan, Azad Naeemi ORCID
This paper was not found in any repository, but could be made available legally by the author.
This paper was not found in any repository, but could be made available legally by the author.

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Abstract

Based on the property of angular dependent transmission probability of electrons observed in graphene PN junctions, a modified MUX-based graphene logic device is introduced. A more elaborate resistance model including ON resistance, leakage resistance and contact resistance is given as well as a capacitance model of the device. Compared with Si CMOS switches, MUX-based logic graphene gates have potentially lower output resistances and a smaller device area. Since interconnects play an ever increasing important role in digital circuit, for the first time, module-level and system-level analyses are made for better evaluating the potential performance of graphene logic devices. Based on the analysis of a 32-bit Han-Carlson adder, module-level evaluation has been done and comparison has been made between graphene logic circuits complemented by multilayer graphene interconnects and CMOS logic circuits with Cu/low k interconnects. The results indicate that MUX-based graphene logic circuits can outperform CMOS circuits in terms of both delay and power consumption. Both devices being evaluated are based on the 15nm technology node. For the system-level analysis, the graphene logic system can have 50% higher throughput than its Si CMOS counterpart with the same power density and die size area.